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ST70135A
ASCOTTM DMT TRANSCEIVER
s DMT
MODEM FOR CPE ADSL, COMPATIBLE WITH THE FOLLOWING STANDARDS: - ANSI T1.413 ISSUE 2 - ITU-T G.992.1 (G.DMT) - ITU-T G.992.2 (G.LITE) 1 & 2) OR BITSTREAM INTERFACE PQFP144 ORDERING NUMBER: ST70135A APPLICATIONS Routers at SOHO, stand-alone modems, PC modems GENERAL DESCRIPTION The ST70135A is the DMT modem and ATM framer of the STMicroelectronics ASCOTTM chipset. When coupled with ST70134 analog front-end and an external controller running dedicated firmware, the product fulfills ANSI T1.413 "Issue 2" DMT ADSL specification. The chip supports UTOPIA level 1 and UTOPIA level 2 interface and a non ATM synchronous bit-stream interface. The ST70135A can be split up into two different sections. The physical one performs the DMT modulation, demodulation, Reed-Solomon encoding, bit interleaving and 4D trellis coding. The ATM section embodies framing functions for the generic and ATM Transmission Convergence (TC) layers. The generic TC consists of data scrambling and Reed Solomon error corrections, with and without interleaving. The ST70135A is controlled and programmed by an external controller (ADSL Transceiver Controller, ATC) that sets the programmable coefficients. The firmware controls the initialization phase and carries out the consequent adaptation operations.
s SUPPORTS EITHER ATM (UTOPIA LEVEL s 16 BIT MULTIPLEXED MICROPROCESSOR
INTERFACE (LITTLE AND BIG ENDIAN COMPATIBILITY)
s ANALOG FRONT END MANAGEMENT s DUAL
LATENCY INTERLEAVED PATHS: FAST AND
s ATM'S PHY LAYER: CELL PROCESSING
(CELL DELINEATION, CELL INSERTION, HEC)
s ADSL'S OVERHEAD MANAGEMENT s REED SOLOMON ENCODE/DECODE s TRELLIS ENCODE/DECODE (VITERBI) s DMT MAPPING/ DEMAPPING OVER 256
CARRIERS
s FINE (2PPM) TIMING RECOVER USING
ROTOR AND ADAPTATIVE FREQUENCY DOMAIN EQUALIZING
s TIME DOMAIN EQUALIZATION s FRONT END DIGITAL FILTERS s 0.35m HCMOS6 TECHNOLOGY s 144 PIN PQFP PACKAGE s POWER CONSUMPTION 1 WATT AT 3.3V
April 2000
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ST70135A
Figure 1 : Block Diagram
TEST SIGNALS CLOCK
TEST MODULE
DATA SYMBOL TIMING UNIT
VCXO
AFE INTERFACE
DSP FRONT-END
FFT/IFFT ROTOR
TRELLIS CODING MAPPER/ DEMAPPER
GENERIC TC REED/ SOLOMON
INTERFACE MODULE
STM UTOPIA
AFE CONTROL
AFE CONTROL INTERFACE
CONTROLLER INTERFACE
ATM SPECIFIC TC
CONTROLLER BUS
GENERAL PURPOSE I/Os
TRANSIENT ENERGY CAPABILITIES ESD ESD (Electronic Discharged) tests have been performed for the Human Body Model (HBM) and for the Charged Device Model (CDM). The pins of ABSOLUTE MAXIMUM RATINGS
Symbol VDD Ptot Tamb Supply Voltage Total Power Dissipation Ambient Temperature 1m/s airflow Parameter
the device are to be able to withstand minimum 2000V for the HBM and minimum 250V for CDM. Latch-up The maximum sink or source current from any pin is limited to 200mA to prevent latch-up.
Minimum 3.0
Typical 3.3 900
Maximum 3.6 1400 70
Unit V mW C
0
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Figure 2 : Pin Connection
SLT_FRAME_S SLT_REQ_S CTRLDATA AFTXED_3 AFTXED_2 AFTXED_1 AFTXED_0 AFRXD_3 AFRXD_2 AFRXD_1 AFRXD_0 AFTXD_3 AFTXD_2 AFTXD_1 AFTXD_0 GP_OUT TESTSE PDOWN
TRSTB
CLWD
MCLK
IDDq
TMS
VDD
VDD
VDD
VDD
VDD
TDO
VSS
VSS
VSS
VSS
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VSS AD_0 AD_1 AD_2 VDD AD_3 AD_4 VSS AD_5 AD_6 VDD AD_7 AD_8 AD_9 VSS AD_10 AD_11 VDD AD_12 VSS PCLK VDD AD_13 AD_14 AD_15 VSS BE1 ALE VDD CSB WR_RDB RDYB OBC_TYPE INTB RESETB VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 VDD 38 U_RXDATA_0 39 U_RXDATA_1 40 VSS 41 U_RXDATA_2 42 U_RXDATA_3 43 VDD 44 U_RXDATA_4 45 U_RXDATA_5 46 VSS 47 U_RXDATA_6 48 U_RXDATA_7 49 VDD 50 U_RX_ADDR_0 51 U_RX_ADDR_1 52 U_RX_ADDR_2 53 U_RX_ADDR_3 54 VSS 55 U_RX_ADDR_4 56 GP_IN0 57 VDD 58 GP_IN1 59 VSS 60 U_RX_REFB 61 U_TX_REFB 62 VDD 63 U_RXCLK 64 U_RXSOC 65 U_RXCLAV 66 U_RXENBB 67 VSS 68 U_TXCLK 69 U_TXSOC 70 U_TX_CLAV 71 U_TXENBB 72 VDD 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 VDD SLT_REQ_F SLT_DAT_S0 SLT_DAT_S1 SLT_DAT_F0 SLT_DAT_F1 VSS SLT_FRAME_F SLAT_CLOCK SLR_VAL_F SLR_DAT_F0 SLR_DAT_F1 SLR_VAL_S VDD SLR_DAT_S0 SLR_DAT_S1 SLR_FRAME_S VSS SLR_FRAME_F U_TX_ADDR_0 U_TX_ADDR_1 U_TX_ADDR_2 VDD U_TX_ADDR_3 U_TX_ADDR_4 U_TX_DATA_0 U_TX_DATA_1 VDD U_TX_DATA_2 U_TX_DATA_3 U_TX_DATA_4 U_TX_DATA_5 VDD U_TX_DATA_6 U_TX_DATA_7 VSS
VSS 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
TCK
ST70135A
TDI
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ST70135A
PIN FUNCTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VSS AD_0 AD_1 AD_2 VDD AD_3 AD_4 VSS AD_5 AD_6 VDD AD_7 AD_8 AD_9 VSS AD_10 AD_11 VDD AD_12 VSS PCLK VDD AD_13 AD_14 AD_15 VSS BE1 ALE VDD CSB WR_RDB RDYB OBC_TYPE INTB RESETB VSS I I OZ I-PD O I VDD VDD VDD VDD VDD VDD IBUF IBUF BT4CR IBUF IBUF IBUF I I O I O I I I VDD VDD IBUF IBUF I C B B B VDD VDD VDD BD8SCR BD8SCR BD8SCR B B B I VDD IBUF I B VDD BD8SCR B B B VDD VDD BD8SCR BD8SCR B B B B B VDD VDD VDD BD8SCR BD8SCR BD8SCR B B B B B VDD VDD BD8SCR BD8SCR B B B B VDD VDD BD8SCR BD8SCR B B B B B VDD VDD VDD Name Type Supply Driver 0V Ground BD8SCR BD8SCR BD8SCR B B B Data 0 Data 1 Address / Data 2 (VSS + 3.3V) Power Supply Address / Data 3 Address / Data 4 0V Ground Address / Data 5 Address / Data 6 (VSS + 3.3V) Power Supply Address / Data 7 Address / Data 8 Address / Data 9 0V Ground Address / Data 10 Address / Data 11 (VSS + 3.3V) Power Supply Address / Data 12 0V Ground Processor clock (VSS + 3.3V) Power Supply Address / Data 13 Address / Data 14 Address / Data 15 0V Ground Address 1 Address Latch (VSS + 3.3V) Power Supply Chip Select Specifies the direction of the access cycle Controls the ATC bus cycle termination ATC Mode Selection (0 = i960; 1 = generic) Requests ATC interrupt service Hard reset 0V Ground BS Function
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PIN FUNCTIONS (continued)
Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 VDD U_RxData_0 U_RxData_1 VSS U_RxData_2 U_RxData_3 VDD U_RxData_4 U_RxData_5 VSS U_RxData_6 U_RxData_7 VDD U_RxADDR_0 U_RxADDR_1 U_RxADDR_2 U_RxADDR_3 VSS U_RxADDR_4 GP_IN_0 VDD GP_IN_1 VSS U_RxRefB U_TxRefB VDD U_Rx_CLK U_Rx_SOC U_RxCLAV U_RxENBB VSS U_Tx_CLK U_Tx_SOC U_TxCLAV U_TxENBB VDD I I OZ I VDD VDD VDD VDD IBUF IBUF BD8SCR IBUF I OZ OZ I VDD VDD VDD VDD IBUF BD8SCR BD8SCR IBUF O I VDD VDD IBUF BT4CR O I I-PD VDD IBUFDQ I I I-PD VDD VDD IBUF IBUFDQ I I I I I I VDD VDD VDD VDD IBUF IBUF IBUF IBUF I I I I OZ OZ VDD VDD BD8SRC BD8SRC B B OZ OZ VDD VDD BD8SRC BD8SRC B B OZ OZ VDD VDD BD8SRC BD8SRC B B OZ OZ VDD VDD BD8SRC BD8SRC B B Name Type Supply Driver BS Function (VSS + 3.3V) Power Supply Utopia RX Data 0 Utopia RX Data 1 0V Ground Utopia RX Data 2 Utopia RX Data 3 (VSS + 3.3V) Power Supply Utopia RX Data 4 Utopia RX Data 5 0V Ground Utopia RX Data 6 Utopia RX Data 7 (VSS + 3.3V) Power Supply Utopia RX Address 0 Utopia RX Address 1 Utopia RX Address 2 Utopia RX Address 3 0V Ground Utopia RX Address 4 General purpose input 0 (VSS + 3.3V) Power Supply General purpose input 1 0V Ground 8kHz clock to ATM device 8kHz clock from ATM device (VSS + 3.3V) Power Supply Utopia RX Clock Utopia RX Start of Cell Utopia RX Cell Available Utopia RX Enable 0V Ground Utopia TX Clock Utopia TX Start of Cell Utopia TX Cell Available Utopia TX Enable (VSS + 3.3V) Power Supply
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PIN FUNCTIONS (continued)
Pin 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 VSS U_TxData_7 U_TxData_6 VDD U_TxData_5 U_TxData_4 U_TxData_3 U_TxData_2 VDD U_TxData_1 U_TxData_0 U_TxADDR_4 U_TxADDR_3 VDD U_TxADDR_2 U_TxADDR_1 U_TxADDR_0 SLR_ FRAME_F VSS SLR_FRAME_S SLR_DATA_S_1 SLR_DATA_S_0 VDD SLR_VAL_S SLR_DATA_F_1 SLR_DATA_F_0 SLR_VAL_F SLAP_CLOCK SLT_FRAME_F VSS SLT_DATA_F_1 SLT_DATA_F_0 SLT_DATA_S_1 SLT_DATA_S_0 SLT_REQ_F VDD I I I I O VDD VDD VDD VDD VDD IBUFDQ IBUFDQ IBUFDQ IBUFDQ BT4CR O O O O O O VDD VDD VDD VDD VDD VDD BT4CR BT4CR BT4CR BT4CR BT4CR BT4CR O O O VDD VDD VDD BT4CR BT4CR BT4CR I I I O VDD VDD VDD VDD IBUF IBUF IBUF BT4CR I I I I I I I VDD VDD VDD VDD IBUF IBUF IBUF IBUF I I I I I I I I VDD VDD VDD VDD IBUF IBUF IBUF IBUF I I I I I I VDD VDD IBUF IBUF I I Name Type Supply Driver BS 0V Ground Utopia TX Data 7 Utopia TX Data 6 (VSS + 3.3V) Power Supply Utopia TX Data 5 Utopia TX Data 4 Utopia TX Data 3 Utopia TX Data 2 (VSS + 3.3V) Power Supply Utopia TX Data 1 Utopia TX Data 0 Utopia TX Address 4 Utopia TX Address 3 (VSS + 3.3V) Power Supply Utopia TX Address 2 Utopia TX Address 1 Utopia TX Address 0 Frame Identifier Fast 0V Ground Receive Frame Identifier Interleaved Receive Data Interleave 1 Receive Data Interleave 0 (VSS + 3.3V) Power Supply Receive Data Valid Indicator Interleaved Receive Data Fast 1 Receive Data Fast 0 Receive Data Valid Indicator Fast Clock for SLAP I/F Transmit Start of frame Indicator Fast 0V Ground Transmit Data Fast 1 Transmit Data Fast 0 Transmit Data Interleave 1 Transmit Data Interleave 0 Transmit Byte Request Fast (VSS + 3.3V) Power Supply Function
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PIN FUNCTIONS (continued)
Pin 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 VSS SLT_REQ_S STL_FRAME_S TDI TDO TMS VDD TCK VSS TRSTB TESTSE GP_OUT PDOWN VDD AFRXD_0 AFRXD_1 AFRXD_2 AFRXD_3 VSS CLWD MCLK CTRLDATA VDD AFTXED_0 AFTXED_1 VSS AFTXED_2 AFTXED_3 VDD IDDq AFTXD_0 AFTXD_1 VSS AFTXD_2 AFTXD_3 VDD O O VDD VDD BT4CR BT4CR O O I O O VDD VDD VDD IBUF BT4CR BT4CR O O VDD VDD BT4CR BT4CR O O O O VDD VDD BT4CR BT4CR O O I I O VDD VDD VDD IBUF IBUF BT4CR I C O I I I I VDD VDD VDD VDD IBUF IBUF IBUF IBUF I I I I I-PD I O O VDD VDD VDD VDD IBUFDQ IBUF BD8SCR BT4CR I-PD VDD IBUFDQ O O I-PU OZ I-PU VDD VDD VDD VDD VDD BT4CR BT4CR IBUFUQ BT4CR IBUFUQ Name Type Supply Driver BS 0V Ground Transmit Byte Request Interleaved Transmit Start of frame Indication Interleaved JTAG I/P JTAG O/P JTAG Made Select (VSS + 3.3V) Power Supply JTAG Clock 0V Ground JTAG Reset none Enables scan test mode O O General purpose output Power down analog front end (Reset) (VSS + 3.3V) Power Supply Receive data nibble Receive data nibble Receive data nibble Receive data nibble 0V Ground Start of word indication Master clock Serial data Transmit channel (VSS + 3.3V) Power Supply Transmit echo nibble Transmit echo nibble 0V Ground Transmit echo nibble Transmit echo nibble (VSS + 3.3V) Power Supply none Test pin, active high O O Transmit data nibble Transmit data nibble 0V Ground Transmit data nibble Transmit data nibble (VSS + 3.3V) Power Supply Function
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ST70135A
I/O DRIVER FUNCTION
Driver BD4CR BD8SCR IBUF IBUFDQ IBUFUQ Function CMOS bidirectional, 4mA, slew rate control CMOS bidirectional, 8mA, slew rate control, Schmitt trigger CMOS input CMOS input, pull down, IDDq control CMOS input, pull up, IDDq control
PIN SUMMARY
Mnemonic Power Supply VDD VSS ATC INTERFACE ALE PCLK CSB BE1 WR_RDB RDYB INTB AD OBC_TYPE I I I I I OZ O IO I-PD C I I I I O O B I 1 1 1 1 1 1 1 16 1 Used to latch the address of the internal register to be accessed Processor clock Chip selected to respond to bus cycle Address 1 (not multiplexed) Specifies the direction of the access cycle Controls the ATC bus cycle termination Requests ATC interrupt service Multiplexed Address/Data bus Select between i960 (0) or generic (1) controller interface (VSS + 3.3V) Power Supply 0V Ground Type BS Type Signals Function
TEST ACCESS PART INTERFACE TDI TDO TCK TMS TRSTB I-PU OZ I-PD I-PU I-PD 1 1 1 1 1 Refer to section
ANALOG FRONT END INTERFACE AFRXD AFTXD AFTXED CLWD PDOWN CTRLDATA MCLK I O O I O O I I O O I O O C 4 4 4 1 1 1 1 Receive data nibble Transmit data nibble Transmit echo nibble Start of word indication Power down analog front end Serial data transmit channel Master cloc
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ST70135A
Mnemonic ATM UTOPIA INTERFACE U_RxData U_TxData U_RxADDR U_TxADDR U_RxCLAV U_TxCLAV U_RxENBB U_TxENBB U_RxSOC U_TxSOC U_RxCLK U_TxCLK U_RxRefB U_TxRefB ATM SLAP INTERFACE SLR_VAL_S SLR_VAL_F SLR_DATA_S SLR_DATA_F SLT_REQ_S SLT_REQ_F SLT_DATA_S SLT_DATA_F SLAP_CLOCK SLR_FRAME_I SLT_FRAME_I SLR_FRAME_F SLT_FRAME_F MISCELLANEOUS GP_IN GP_OUT RESETB TESTSE IDDq
Type
BS Type Signals
Function
OZ I I I OZ OZ I-TTL I-TTL OZ I-TTL I-TTL I-TTL O I-TTL
B I I I O O I I O I C C O I
8 8 5 5 1 1 1 1 1 1 1 1 1 1
Receive interface Data Transmit interface Data Receive interface Address Transmit interface Address Receive interface Cell Available Transmit interface Cell Available Receive interface Enable Transmit interface Enable Receive interface Start of Cell Transmit interface Start of Cell Receive interface Utopia Clock Transmit interface Utopia Clock 8kHz reference clock to ATM device 8kHz reference clock from ATM device
O O O O O O I I O O O O O
1 1 2 2 1 1 2 2 1 1 1 1 1
I-PD O I I I
I O I none none
2 1 I none none
General purpose input General purpose output Hard reset Enable scan test mode Test pin, active high
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I I-PU = Input, CMOS levels = Input with pull-up resistance, CMOS levels I-PD = Input with pull-down resistance, CMOS levels I-TTL = Input TTL levels O = Push-pull output OZ = Push-pull output with high-impedance state IO = Input / Tristate Push-pull output BS cell = Boundary-Scan cell I = Input cell O = Output cell B = Bidirectional cell C = Clock Main Block Description The following drawings describe the sequence of functions performed by the chip. DSP Front-End The DSP Front-End contains 4 parts in the receive direction: the Input Selector, the Analog Front-End Interface, the Decimator and the Time Equalizer. The input selector is used internally to enable test loopbacks inside the chip. The Analog Front-End lnterface transfers 16-bit words, multiplexed on 4 input/output signals. Word transfer is carried out in 4 clock cycles. The Decimator receives 16-bit samples at 8.8MHz (as sent by the Analog Front-End chip: ST70134) and reduces this rate to 2.2MHz. Figure 3 : DSP Front-End Receive
BYPASS
The Time Equalizer (TEQ) module is a FIR filter with programmable coefficients. Its main purpose is to reduce the effect of Inter-Symbol Interferences (ISI) by shortening the channel impulse response. Both the Decimator and TEQ can be bypassed. In the transmit direction, the DSP Front-End includes: sidelobe filtering, clipping, delay equalization and interpolation. The sidelobe filtering and delay equalization are implemented by IIR Filters, reducing the effect of echo in FDM systems. Clipping is a statistical process limiting the amplitude of the output signal, optimizing the dynamic range of the AFE. The interpolator receives data at 2.2MHz and generates samples at a rate of 8.8MHz. DMT Modem This module is a programmable DSP unit. Its instruction set enables the basic functions of the DMT algorithm like FFT, IFFT, Scaling, Rotor and Frequency Equalization (FEQ) in compliance with ANSI T1.413 specifications. In the RX path, the 512-point FFT transforms the time-domain DMT symbol into a frequency domain representation which can be further decoded by the subsequent demapping stages.
In other words, the Fast Fourier Transform process is used to transform from time domain to frequency domain (receive path). 1024 time samples are processed. After the first stage time domain equalization and FFT block an ICI (InterCarrier Interference) free information stream turns out.
From Analog Front-end
IN SELECT
AFE I/F
DEC
TEC
To DMT Modem
Figure 4 : DSP Front-End Transmit
From DMT Modem
FILTERING CLIPPING DELAY EQUALIZER
INTERPOLATOR
AFE I/F
OUT SELECT
To Analog Front End
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Figure 5 : DMT Modem (Rx & Tx)
TREILLIS CODING DECODING
To/From DSP FE
FFT IFFT
FEQ FTG
ROTOR
MAPPER DEMAPPER
To/From TC
FEQ COEFFICIENTS
MONITOR
FEQ Update
Monitor Indications
This stream is still affected by carrier specific channel distortion resulting in an attenuation of the signal amplitude and a rotation of the signal phase. To compensate, a Frequency domain equalizer (FEQ) and a Rotor (phase shifter) are implemented. The frequency domain equalization performs an operation on the received vector in order to match it with the associated point in the constellation. The coefficient used to perform the equalization are floating point, and may be updated by hardware or software, using a mechanism of active and inactive table to avoid DMT synchro problems.In the transmit path, the IFFT reverses the DMT symbol from frequency domain to time domain. The IFFT block is preceded by Fine Tune Gain (FTG) and Rotor stages, allowing for a compensation of the possible frequency mismatch between the master clock frequency and the transmitter clock frequency (which may be locked to another reference). The Inverse Fast Fourier Transform process is used to transform from frequency domain to time domain (transmit path). 256 positive frequencies are processed, giving 512 samples in the time domain. The FFT module is a slave DSP engine controlled by the firmware running on an external controller. It works off line and communicates with other blocks through buffers controlled by the "Data Symbol Timing Unit". The DSP executes a program stored in a RAM area, which constitutes
a flexible element that allows for future system enhancements. DPLL The Digital PLL module receives a metric for the phase error of the pilot tone. In general, the clock frequencies at the ends (transmitter and receiver) do not match exactly. The phase error is filtered and integrated by a low pass filter, yielding an estimation of the frequency offset. Various processes can use this estimate to deal with the frequency mismatch. In particular, small accumulated phase error can be compensated in the frequency domain by a rotation of the received code constellation (Rotor). Larger errors are compensated in the time domain by inserting or deleting clock cycles in the sample input sequence. Eventually that leads to achieve less than 2ppm between the two ends. Mapper/Demapper, Monitor, Trellis Coding, FEQ Update The Demapper converts the constellation points computed by the FFT to a block of bits. This means to identify a point in a 2D QAM constellation plane. The Demapper supports Trellis coded demodulation and provides a Viterbi maximum likelihood estimator. When the Trellis is active, the Demapper receives an indication for the most likely constellation subset to be used.
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ST70135A
In the transmit direction, the mapper receives a bit stream from the Trellis encoder and modulates the bit stream on a set of carriers (up to 256). It generates coordinates for 2n QAM constellation, where n < 15 for all carriers. The Mapper performs the inverse operation, mapping a block of bits into one constellation point (in a complex x+jy representation) which is passed to the IFFT block. The Trellis Encoder generates redundant bits to improve the robustness of the transmission, using a 4-Dimensional Trellis Coded Modulation scheme. This feature can be disabled.The Monitor computes error parameters for carriers specified in the Demapper process. Those parameters can be used for updates of adaptive filters coefficients, clock phase adjustments, error detection, etc. A series of values is constantly monitored, such as signal power, pilot phase deviations, symbol erasures generation, loss of frame, etc. Generic TC Layer Functions These functions relate to byte oriented data streams. They are completely described in ANSI T 1.4 13. Additions described in the Issue 2 of this specification are also supported. The data received from the demapper may be split into two paths, one dedicated to an interleaved data flow the other one for a fast data flow. No external RAM is needed for the interleaved path. The interleaving/deinterleaving is used to increase the error correcting capability of block codes for error bursts. After deinterleaving (if applicable), the data flow enters a Reed-Solomon error correcting code decoder, able to correct a Figure 6 : Generic TC Layer Functions
IndicationBits AOC EOC
number of bytes containing bit errors. The decoder also uses the information of previous receiving stages that may have detected the error bytes and have labelled them with an "erasure indication". Each time the RS decoder detects and corrects errors in a RS codeword, an RS correction event is generated. The occurrence of such events can be signalled to the management layer.After the RS decoder, the corrected byte stream is descrambled in the PMD (Physical Medium Dependent) descramblers. Two descramblers are used, for interleaved and non-interleaved data flows. These are defined in ANSI T1.413. After descrambling, the data flows enter the Deframer that extracts and processes bytes to support Physical layer related functions according to ANSI T1.413. The ADSL frames indeed contain physical layer-related information in addition to the data passed to the higher layers. In particular, the deframer extracts the EOC (Embedded Operations Channel), the AOC (ADSL Overhead Control) and the indicators bits and passes them to the appropriate processing unit (e.g. the transceiver controller). The deframer also performs a CRC check (Cyclic Redundancy Check) on the received frame and generates events in case of error detection.Event counters can be read by management processes. The outputs of the deframer are an interleaved and a fast data streams. These data streams can either carry ATM cells or another type of traffic. In the latter case, the ATM specific TC layer functional block, described hereafter, is bypassed and the data stream is directly presented at the input of the interface module.
To/From Demapper
FAST DATA PATX MERGER RS CODING DECODING
F
PMD SCRAMBLER DESCRAMBLER PMD SCRAMBLER DESCRAMBLER
F FRAMER DEFRAMER To ATM TC
INTERLEAVER DE-INTERLEAVER
I
I
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ST70135A
ATM Specific TC Layer Functions The 2 bytes streams (fast and slow) are received from the byte-based processing unit. When ATM cells are transported, this block provides basic cell functions such as cell synchronization, cell payload descrambling, idle/unassigned cell filter, cell Header Error Correction (HEC) and detection. The cell processing happens according to ITU-T I.163 standard. Provision is also made for BER measurements at this ATM cell level. When non cell oriented byte streams are transported, the cell processing unit is not active. Figure 7 : ATM Specific TC Layer Functions The interface module collects cells (from the cell-based function module) or a Byte stream (from the deframer). Cells are stored in FIFO's (424 bytes or 8 cell wide, transmit buffers have the same size), from which they are extracted by 2 interface submodules, one providing a Utopia level 1 interface and the other a Utopia level 2 interface.Byte stream are dumped on the SLAP (Synchronous Link Access Protocol) interface. Only one type of interface can be enabled in a specific configuration.
BER
From Generic TC
FAST
CELL SCRAMBLER DESCRAMBLER SYNCHRONIZER
HEC
CELL INSERTION/ FILTER
To Interface Module
SLOW
CELL SCRAMBLER DESCRAMBLER SYNCHRONIZER
HEC
CELL INSERTION/ FILTER
BER
Figure 8 : Interface Module
FAST BYTE STREAM SLAP LEVEL 1
UTOPIA FAST ATM
UTOPIA From ATM TC SLOW ATM
LEVEL 2
UTOPIA
LEVEL 1
UTOPIA SLOW BYTE STREAM SLAP
LEVEL 2
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ST70135A
DMT Symbol Timing Unit (DSTU) The DSTU interfaces with various modules, like DSP FrontEnd, FFT/IFFT, Mapper/Demapper RS, , Monitor and Transceiver Controller. It consists of a real time and a scheduler modules. The real time unit generates a timebase for the DMT symbols (sample counter), superframes (symbol counter) and hyper-frames (sync counter). The timebases can be modified by various control features. They are continuously fine-tuned by the DPLL module. The DSTU schedulers execute a program, controlled by program opcodes and a set of variables, the most important of which are real time counters. The transmit and receive sequencers are completely independent and run different programs. An independent set of variables is assigned to each of them. The sequencer programs can be updated in real time. ST70135A interfaces Data and addresses are multiplexed ST70135A works in 16 bits data access, so address bit 0 is not used. Address bit 1 is not multiplexed with data. It has its own pin : BE1. Byte access are not supported. Access cycle read or write are always in 16 bits data wide, ie bit address A0 is always zero value. The interrupt request pin to the processor is INTB, and is an Open Drain output. The ST70135A supports both little and big endian. The default feature is big endian. Figure 9 : ST70135A Interfaces
AFE INTERFACE TO ADSL LINE (ST70134) RESET JTAG CLOCK
ST70135A
PROCESSOR INTERFACE (ATC)
Overview See Figure 9. Processor Interface (ATC) The ST70135A is controlled and configured by an external processor across the processor interface. All programmable coefficients and parameters are loaded through this path.
DIGITAL INTERFACE UTOPIA/BITSTREAM INTERFACE
Generic Interface This interface is suitable for a number of processors using a multiplexed Address/data bus. In this case, synchronization of the input signals with PCLK pin is not necessary.
Figure 10 : Generic Processor Interface Write Timing Cycle
Talew ALE Twr2cs CSB Tavs Tavh AD(15-0) Tale2cs WRB Tcs2rdy READY Tcs2wr Twrw Twr2d Twdvd Tmclk Tdvh
RDB
T csre
Trdy2wr
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ST70135A
Figure 11 : Generic Processor Interface Read Timing Cycle
Talew ALE Trd2cs CSB Tavs Tavh AD(15-0) Tale2cs RDB Twr2d Twdvd Tcsrd Tmclk READY T csrs WRB T csre Trdy2dr Twrw Tdvh T ale2Z
Generic processor interface Cycle Timing
All AC characteristics are indicated for a 100pF capacitive load.
Symbol tr & tf Talew Tavs Tavh Tale2cs Tale2Z Tcs2rdy Tcsre Tcs2wr Twr2d Trdy2wr Tdvs Tdvh Twr2cs Tcs2rd Trdy2rd Trd2cs Tmclk Parameters Rise & Fall time (10% to 90%) ALE pulse width Address Valid setup time Address Valid Hold time ALE to CSB ALE to high Z state of address bus CSB to RDYB asserted Access Time CSB to WRB WRB to data RDYB to WRB data setup time data hold time WRB to CSB CSB to RDB RDY to RDB RDB to CSB Master clock Timing 0 10 1/2Tmclk -10 0 0 -10 Tmclk 0 15 12 10 10 0 50 60 900 Minimum Typical Maximum 3 Unit ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns
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ST70135A
Generic Processor Interface Pins and Functional Description
Name AD[0..15] ALE RDB WRB CSB RDYB INTB Type I/O I I I I OZ O Function Multiplexed address / data bus Address Latch Enable Read cycle indication Write cycle indication Chip Select Bus cycle ready indication Interrupt
PHY RECEIVE
Figure 12 : Receive Interface
PHY RxREF* RxCLAV RxENB* RxCLK RxDATA 8 RxSOC CELL RECEIVE ATM
Figure 13 : Transmit Interface
Digital interface ATM or serial
Digital Interface before modulation demodulation. for data to the loop and from the loop after
PHY TxREF* TxCLAV TxENB* PHY TRANSMIT TxCLK TxDATA TxSOC 8
ATM LAYER
This interface collects cells (from the cell based function module) or a byte stream (from the deframer). Cells are stored in a fifo, 2 interfaces submodules can extract data from the fifo. Byte streams are dumped on the bitstream interface (with no fifo). 3 kinds of interface are allowed: - Utopia Level 1 - Utopia Level 2 - Bitstream based on a proprietary exchange The interface selection is programmed by writing the Utopia PHY address register. Only one interface can be enabled in a ST70135A configuration. Utopia Level 1 supports only one PHY device. Utopia Level 2 supports multi-PHY devices (See Utopia Level 2 specifications). Each buffer provides storage for 8 ATM cells (both directions for Fast and Interleaved channel). The Utopia Level 2 supports point to multipoint configurations by introducing an addressing capability and by making distinction between polling and selecting a device.
CELL TRANSMIT
Utopia Level 1 Interface The ATM forum takes the ATM layer chip as a reference. It defines the direction from ATM to physical layer as the Transmit direction. The direction from physical layer to ATM is the Receive direction. Figures 12 & 13 show the interconnection between ATM and PHY layer devices, the optional signals are not supported and not shown. The Utopia interface transfers one byte in a single clock cycle, as a result cells are transformed in 53 clock cycles. Both transmit and receive are synchronized on clocks generated by the ATM layer chip, and no specific relationship between receive and transmit clocks is required. In this mode, the ST70135A can only support one data flow : either interleaved or fast.
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ST70135A
Figure 14 : Timing (Utopia 1 Receive Interface)
RxCLK RxSOC
RxENB
RxDATA
X
H1
H2
P44
P45
P46
P47
P48
X
RxCLAV
Pin Description
Name RxClav RxEnb 1 Type O I Meaning Receive Cell available Receive Enable Usage Signals to the ATM chip that the ST70135A has a cell ready for transfer Signals to the ST70135A that the ATM chip will sample and accept data during next clock cycle Gives the timing signal for the transfer, generated by ATM layer chip. ATM cell data, from ST70135A chip to ATM chip, byte wide. Rx Data [7] is the MSB. Identifies the cell boundary on RxData Indicate to the ATM layer chip that RxData contains the first valid byte of a cell. Active low signal Remark Remains active for the entire cell transfer RxData and RxSOC could be tri-state when RxEnb* is inactive (high). Active low signal
RxClk RxData RxSOC
I O O
Receive Byte Clock Receive Data (8bits) Receive Start Cell
RxRef 1
Note
O
Reference Clock
8 kHz clock transported over the network
1. Active low signal
When RxEnb is asserted, the ST70135A reads data from its internal fifo and presents it on RxData and RxSOC on each low-to-high transition of RxClk, ie the ATM layer chip samples all RxData and RxSOC on the rising edge of RxSOC on the rising edge of RxClk. Pin Description
Name TxClav TxEnb 1 TxClk TxData TxSOC TxRef 1
Note
Type O I I I I I
Meaning Transmit Cell available Transmit Enable Transmit Byte Clock Transmit Data (8bits) Transmit Start of Cell Reference Clock
Usage
Remark
Signals to the ATM chip that the physical Remains active for the entire layer chip is ready to accept a complete cell cell transfer Signals to the ST70135A that TxData and TxSOC are valid Gives the timing signal for the transfer, generated by ATM layer chip.
ATM cell data, from ATM layer chip to ST70135A, byte wide. TxData [7] is the MSB.
Identifies the cell boundary on TxData 8kHz clock from the ATM layer chip TxData contains the first valid byte of the cell.
1. Active low signal
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ST70135A
The ST70135A samples TxData and TxSOC signals on the rising edge of TxClk, if TxEnb is asserted. TxClk, RxClk, AC Electrical Characteristics
Symbol F Tc Tj Trf L Parameters Clock frequency Clock duty cycle Clock peak to peak jitter Clock rise fall time Load Min 1.5 40 Max 25 60 5 4 100 Unit MHz % % ns pF T11 T9 Signal going low impedance to RxClk Signal going High impedance to RxClk Signal going low impedance to RxClk Signal going High impedance to RxClk Load 10 ns
RxData, RxSOC, RxClav AC Electrical Characteristics
Symbol T7 T8 Parameters Input set-up time to TxClk Hold time to Tx Clk Min 10 1 Max Unit ns ns
T10
0
ns
TxData, TxSOC, AC Electrical Characteristics
Symbol T5 T6 L Parameters Input set-up time to TxClk Hold time to TxClk Load Min 10 1 100 Max Unit ns ns pF
1
ns
T12
1
ns
L
100
pF
Figure 15 : Timing (Utopia 1 Transmit Interface)
TxCLK TxSOC
TxENB
TxDATA
X
H1
H2
P44
P45
P46
P47
P48
X
TxCLAV
Figure 16 : Timing Specification (Utopia 1)
Clock T5, T7 Signal (at input) Signal (highz) T11 T9 T12 T10 T6, T8
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ST70135A
DIGITAL INTERFACE Utopia Level 2 Interface The ATM forum takes the ATM layer chip as a reference. It defines the direction from ATM to physical layer as the Transmit direction. The direction from physical layer to ATM is the Receive direction. Figure 17 shows the interconnection between ATM and PHY layer devices, the optional signals are not supported and not shown. The UTOPIA interface transfers one byte in a single clock cycle, as a result cells are transferred in 53 clock cycles.Both transmit and receive interfaces are synchronized on clocks generated by the ATM layer chip, and no specific relationship between Receive and Transmit clock is assumed, they must be regarded as mutually asynchronous clocks. Flow control signals are available to match the bandwidth constraints of the physical layer and the ATM layer. The UTOPIA level 2 supports point to multipoint configurations by introducing on addressing capability and by making a distinction between polling and selecting a device: - The ATM chip polls a specific physical layer chip by putting its address on the address bus when the Enb* line is asserted. The addressed physical layer answers the next cycle via the Clav line reflecting its status at that time. - The ATM chip selects a specific physical layer by putting its address on the address bus when the Enb* line is deasserted and asserting the Enb* line on the next cycle. The addressed physical layer chip will be the target or source of the next cell transfer (see Figure 17). Utopia Level 2 Signals The physical chip sends cell data towards the ATM layer chip. The ATM layer chip polls the status of the fifo of the physical layer chip. The cell exchange proceeds like: a) The physical layer chip signals the availability of a cell by asserting RxClav when polled by the ATM chip. b) The ATM chips selects a physical layer chip, then starts the transfer by asserting RxEnb*. c) If the physical layer chip has data to send, it puts them on the RxData line the cycle after it sampled RxEnb* active. It also advances the offset in the cell. If the data transferred is the first byte of a cell, RxSOC is 1b at the time of the data transfer, 0b otherwise. d) The ATM chip accepts the data when they are available. If RxSOC was 1b during the transfer, it resets its internal offset pointer to the value 1, otherwise it advances the offset in the cell. Figure 17 : Signal at Utopia Level 2 Interface
PHY ATM
RxADDR 5 RxCLAV 1 RxENB* PHY RECEIVE RxCLK RxDATA 8 RxSOC RxREF* ATM RECEIVE
TxADDR 5 TxCLAV 1 TxENB* PHY TRANSMIT TxCLK TxDATA 8 TxSOC TxREF* ATM TRANSMIT
ST70135A Utopia Level 2 MPHY Operation Utopia level 2 MPHY operation can be done by various interface schemes. The ST70135A supports only the required mode, this mode is referred to as "Operation with 1 TxClav and 1 RxClav". PHY Device Identification The ST70135A holds 2 PHY layer Utopia ports, one is dedicated to the fast data channel, the other one to the interleaved data channel. The associated PHY address is specified by the PHY_ADDR_x fields in the Utopia PHY address register.
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ST70135A
Beware that an incorrect address configuration may lead to bus conflicts. A feature is defined to disable (tri-state) all outputs of the Utopia interface. It is enabled by the TRI_STATE_EN bit in the Rx_interface control register. Pin Description Utopia 2 (Receive Interface)
Name RxClav Type O Meaning Receive Cell available Usage Signals to the ATM chip that the STLC60135 has a cell ready for transfer Signals to the physical layer that the ATM chip will sample and accept data during next clock cycle Gives the timing signal for the transfer, generated by ATM layer chip. ATM cell data, from physical layer chip to ATM chip, byte wide. Identifies the cell boundary on RxData Use to select the port that will be active or polled 8kHz clock transported over the network Indicate to the ATM layer chip that RxData contains the first valid byte of a cell. Remark Remains active for the entire cell transfer RxData and RxSOC could be tri-state when RxEnb* is inactive (high)
RxEnb*
I
Receive Enable
RxClk
I
Receive Byte Clock
RxData
O
Receive Data (8 bits)
RxSOC
O
Receive Start Cell
RxAddr RxRef *
I O
Receive Address (5 bits) Reference Clock
*Active low signal Pin Description Utopia 2 (Transmit interface)
Name TxClav Type O Meaning Transmit Cell available Usage Signals to the ATM chip that the physical layer chip is ready to accept a cell Signals to the physical layer that TxData and TxSOC are valid Gives the timing signal for the transfer, generated by ATM layer chip. ATM cell data, to physical layer chip to ATM chip, byte wide. Identifies the cell boundary on TxData Use to select the port that will be active or polled 8kHz clock from the ATM layer chip Remark Remains active for the entire cell transfer
TxEnb*
I
Transmit Enable
TxClk
I
Transmit Byte Clock
TxData TxSOC TxAddr TxRef *
I I I I
Transmit Data (8 bits) Transmit Start of Cell Transmit Address (5 bits) Reference Clock
*Active low signal
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ST70135A
BitStream Interface The Bitstream interface is a proprietary point to point interface. The ST70135A is the bus master of the interface. The interface is synchronous, a common clock is used. SLAP (Synchronous Link Access Protocol) Interface The SLAP interface is a point to point bitstream interface. The ST70135A is the bus master of the interface. The interface is synchronous, a common clock (SLAP_CLOCK) is used. The basic idea is illustrated in Figure 17. The SLAP interface dumps the data of the fast and interleaved channels on 2 separate sub interfaces. The data flow from the SLAP interface must be enabled by the Transceiver Controller. A disabled cell interface does not dump data on its interface. Figure 18 : Common Clock Data Transfer
Source Rising Clock D Q Falling Clock D Q
Receive SLAP Interface The interface signals use 2 signal types: (refer to Figure 19) - SLR_DATA [1:0]: data pins, a byte is transferred in 4 cycles of 2 bits. The msb are transmitted first, odd bits are asserted on SLR_DATA [1]. - SLR_VAL: indicates the data transfer and the byte boundary - SLR_FRAME: indicates the start of a superframe Notice 2 SLAP interfaces are supported, one for the fast data flow, the other one for the interleaved data flow. The logic timing diagram is shown in Figure 20. Figure 19 : Receive Path, SLAP Interface
DATA EXTERNAL COMPONENT (SLAVE) VALID FRAME 2 MODEM (MASTER)
CK QN
CK QN
Sink
SLAP_CLOCK
SLAP_CLOCK
Figure 20 : Receive SLAP Interface Timing
STM_CLOCK 0 1 2 3 8
Minimum 8 cycles FRAME Undefined Undefined
VALID SLR_VAL must not repeat in a 8 clock period SLR_DATA(1) SLR_DATA(0) b7 b6 b5 b4 b3 b2 b1 b0 One byte as 4 times 2 bits
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ST70135A
The implementation must guarantee that all active SLR_Valid signals must be separated by at least 8 clock cycles. Refer to Figure 20. The SLR_FRAME signals are asserted when the first pair of bits of a frame are transferred. For the fast channel a frame is defined as a superframe timebase. For the interleaved channel the frame is defined by a timebase period of 4 superframes. Both timebases are synchronized to the data flow.
Both timebases are synchronized to the data flow and guarantee that the frame indication is asserted when the first bits of the first DMT symbol are transferred. Figure 21 : Interface Towards PHY Layer
REQUEST EXTERNAL COMPONENT (SLAVE) 2 DATA FRAME MODEM (MASTER)
Transmit SLAP Interface The Transmit interface uses the following signals (refer to Figure 21): - SLT_REQ: byte request. - SLT_FRAME: start of frame indication. - SLT_DATA [1:0] data pins, a byte is transferred 2 bits at the time in 4 successive clock cycles. MSB first, odd bits on SLT_DATA [1]. The logical timing diagram is shown in Figure 22. The delay between Request and the associated data byte is defined as 8 cycles. The SLT_FRAME signals are asserted when the first pair of bits of a frame are transferred. For the fast channel a frame is defined as a superframe timebase. For the interleaved channel the frame is defined by a timebase period of 4 superframes. Figure 23 : Transmit SLAP Interface Timing Diagram
CLOCK 0 8 9 0 SLT_REQUEST 1
CLOCK
Figure 22 : Interface Timing
Tper Th CLOCK Ts ALL INPUTS Td ALL OUTPUTS Tl
Thd
1 1
1 2
STM_CLOCK Request may be repeated after 4 cycles Delay Request-data equals 8 cycles
SLT_DATA(1)
SLT_DATA(0) SLT_FRAME
b5 b3 b1 b7 One byte in 4 cycles b6 b4 b2 b0
Repeated each superframe/ S-frame Undefined
Undefined
SLAP INTERFACE, AC Electrical Characteristics
Symbol Tper Th Tl Ts Thd Td 22/29 Parameter Clock Period Clock High Clock Low Setup Hold Data Delay 20pF load Test Conditi on Refer to MCLK 11 11 3 2 3 6 Minimum Typical Maximum Unit ns ns ns ns ns ns
ST70135A
Analog Front End Control Interface The Analog Front End Interface is designed to be connected to the ST70134 Analog Front End component. Transmit Interface The 16 bit words are multiplexed on 4 AFTXD output signals. As a result 4 cycles are needed to transfer 1 word. Refer to table 1 for the bit/pin allocation for the 4 cycles. The first of 4 cycles is identified by the CLWD signal. Refer to Figure 23. Figure 24 : Transmit Word Timing Diagram
MCLK
The ST70135A fetches the 16 bit word to be multiplexed on AFTXD from the Tx Digital Front-End module. Receive Interface The 16 bit receive word is multiplexed on 4 AFRXD input signals. As a result 4 cycles are needed to transfer 1 word. Refer to Table 2 for the bit / pin allocation for the 4 cycles. The first of 4 cycles is identified by the CLWD must repeat after 4 MCLK cycles.
CLWD
AFTXD AFTXED Cycle0 GP_OUT Test0 Test1 Test2 Test3 Cycle1 Cycle2 Cycle3
Figure 25 : Receive Word Timing Diagram
MCLK
CLWD
AFRXD Cycle0 GP_IN(0) Test0 Test1 Test2 Test3 Cycle1 Cycle2 Cycle3
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ST70135A
Figure 26 : Transmit Interface Table 1 : Transmitted Bits Assigned to Signal / Time Slot
Cycle 0
Tv AFTXD AFTXED Tc CLWD
MCLK
Cycle 1 b4 b5 b6 b7 t1
Cycle 2 b8 b9 b10 b11 t2
Cycle 3 b12 b13 b14 b15 t3
AFTXD[0] AFTXD[1] AFTXD[2] AFTXD[3] GP_OUT
b0 b1 b2 b3 t0
Figure 27 : Receive Interface
Table 2 : Transmitted Bits Assigned to Signal / Time Slot
Cycle 0 Cycle 1 b4 b5 b6 b7 t1 Cycle 2 b8 b9 b10 b11 t2 Cycle 3 b12 b13 b14 b15 t3
MCLK Ts Th AFRXD
AFRXD[0] AFRXD[1] AFRXD[2] AFRXD[3] GP_IN
b0 b1 b2 b3 t0
Table 3 : Master Clock (MCLK) AC Electrical Characteristics
Symbol F Tper Th Parameter Clock Frequency Clock Period Clock Duty Cycle 40 Minimum Typical 35.328 28.3 60 Maximum Unit MHz ns %
Table 4 : AFTXD, AFTXED, CLWD AC Electrical Characteristics
Symbol Tv Tc Parameter Data Valid Time Data Valid Time Minimum 0 0 Typical Maximum 10 10 Unit ns ns
Table 5 : AFRXD AC Electrical Characteristics
Symbol Ts Th Parameter Data setup Time Data hold Time Minimum 5 5 Typical Maximum Unit ns ns
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ST70135A
Tests, Clock, JTAG Interface - Mclk: Master Clock (35.328MHz) generated by VCXO - ATM receive interface, asynchronous clock generated by Utopia Master - ATM transmit interface, asynchronous clock generated by Utopia Master - ATC clock (Pclk): external asynchronous clock (synchronous with ATC in case of i960 specific interface) JTAG TP interface: Standard Test Access Port, Used with the boundary scan for chip and board testing. This JTAG TAP interface consists in 5 signals: TDI, TDO, TCK & TMS. TSRTB: Test Reset, reset the TAP controller. TRSTB is an active low signal. Table 6 : Boundary Scan Chain Sequence
Sequence Number 2 3 4 6 7 9 10 12 13 14 16 17 19 21 23 24 25 27 28 30 31 32 Mnemonic AD_0 AD_1 AD_2 AD_3 AD_4 AD_5 AD_6 AD_7 AD_8 AD_9 AD_10 AD_11 AD_12 PCLK AD_13 AD_14 AD_15 BE1 ALE CSB WR_RDB RDYB Pin BS Type B B B B B B B B B B B B B I B B B I C I I O
Table 6 : Boundary Scan Chain Sequence
Sequence Number 33 34 35 38 39 41 42 44 45 46 47 48 50 51 52 53 55 56 58 60 61 63 64 65 66 68 69 70 71 74 75 77 78 79 80 82 Mnemonic OBC_TYPE INTB RESETB U_RxData_0 U_RxData_1 U_RxData_2 U_RxData_3 U_RxData_4 U_RxData_5 VSS U_RxData_6 U_RxData_7 U_RxADDR_0 U_RxADDR_1 U_RxADDR_2 U_RxADDR_3 U_RxADDR_4 GP_IN_0 GP_IN_1 U_RxRefB U_TxRefB U_RxCLK U_RxSOC U_RxCLAV U_RxENBB U_TxCLK U_TxSOC U_TxCLAV U_TxENBB U_TxData_7 U_TxData_6 U_TxData_5 U_TxData_4 U_TxData_3 U_TxData_2 U_TxData_1 I I I I I I I B B I I I I I i I O I Pin BS Type I O I B B B B B B
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ST70135A
Table 6 : Boundary Scan Chain Sequence
Sequence Number 83 84 85 87 88 89 90 92 93 94 96 97 98 99 100 101 103 104 105 106 107 110 111 112 113 114 116 118 119 120 121 123 124 125 Mnemonic U_TxData_0 U_TxADDR_4 U_TxADDR_3 U_TxADDR_2 U_TxADDR_1 U_TxADDR_0 SLR_FRAME_F SLR_FRAME_S SLR_DATA_S_1 SLR_DATA_S_0 SLR_DATA_S SLR_DATA_F_1 SLR_DATA_F_0 SLR_VAL_F SLAP_CLOCK SLT_FRAME_F SLT_DATA_F_1 SLT_DATA_F_0 SLT_DATA_S_1 SLT_DATA_S_0 SLT_REQ_F SLT_REQ_S SLT_FRAME_S TDI TDO TMS TCK TRSTB TESTSE GP_OUT PDOWN AFRXD_0 AFRXD_1 AFRXD_2 none O O I I I Bits from 3 to 15 are reserved GP_OUT RW [2] 1 Field GP_IN Type R Position Bits [0,1] Length 2 Function Sampled level on pins GP_IN Output level on pins GP_OUT Pin BS Type I I I I I I
Table 6 : Boundary Scan Chain Sequence
Sequence Number 126 128 129 130 132 133 135 136 138 139 140 142 143 Mnemonic AFRXD_3 CLWD MCLK CTRLDATA AFTXED_0 AFTXED_1 AFTXED_2 AFTXED_3 IDDq AFTXD_0 AFTXD_1 AFTXD_2 AFTXD_3 1 1 1 Pin BS Type I I C O O O O O none O O O O
General purpose I/O register 2 general Purpose Register (0x040)
Reset Initialization The ST70135A supports two reset modes: - A 'hardware' reset is activated by the RESETB pin (active low). A hard reset occurs when a low input value is detected at the RESETB input. The low level must be applied for at least 1ms to guarantee a correct reset operation. All clocks and power supplies must be stable for 200ns prior to the rising edge of the RESETB signal. - 'Soft' reset activated by the controller write access to a soft reset configuration bit. The reset process takes less than 10000 MCLK clock cycles.
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ST70135A
ELECTRICAL SPECIFICATIONS Generic DC Electrical Characteristics The values presented in the following table apply for all inputs and/or outputs unless otherwise specified. Specifically they are not influenced by the choice between CMOS or TTL levels. All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device. IO Buffers Generic DC Characteristics
Symbol IIN IOZ IPU IPD RPU RPD Parameter Input Leakage Current Test Condition VIN = VSS, VDD no pull up /pull down VIN = VSS, VDD no pull up /pull down VIN = VSS VIN = VDD VIN = VSS VIN = VDD Minimu m -1 -1 -25 25 -66 66 50 50 Typical Maximum 1 1 -125 125 Unit
A A
mA mA K K
Tristate Leakage Current
Pull up Current Pull Down Current Pull up Resistance Pull Down Resistance
Input / Output CMOS Generic Characteristics
The values presented in the following table apply for all CMOS inputs and/or outputs unless otherwise specified.
CMOS IO Buffers Generic Characteristics
Symbol VIL VIH VHY VOL VOH Parameter Test Condition Minimum Typical Maximum 0.2 x VDD 0.8 x VDD Slow edge < 1V/s, only for SCHMITx IOUT = XmA* IOUT = XmA* 0.85 x VDD 0.8 0.4 Unit V V V V V
Low Level Input Voltage High Level Input Voltage
Schmitt trigger hysteresis Low Level Output Voltage High Level Output Voltage
*Note The reference current is dependent on the exact buffer chosen and is a part of the buffer name. The available values are 2, 4 and 8mA.
Input/ Output TTL Generic Characteristics The values presented in the following table apply for all TTL inputs and/or outputs unless otherwise specified.
Symbol VIL VIH VILHY VIHHY VHY VOL VOH Parameter Low Level Input Voltage High Level Input Voltage Low Level Threshold, falling High Level Threshold, rising Schmitt Trigger Hysteresis Low Level Output Voltage High Level Output Voltage Slow edge < 1V/s Slow edge < 1V/s Slow edge < 1V/s IOUT = XmA* IOUT = XmA* 2.4 2.0 0.9 1.3 0.4 1.35 1.9 0.7 0.4 Test Conditio n Minimum Typical Maximum 0.8 Unit V V V V V V V
*Note The reference current is dependent on the exact buffer chosen and is a part of the buffer name. The available values are 2, 4 and 8mA.
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ST70135A
PQFP144 PACKAGE MECHANICAL DATA Figure 28 : Package Outline PQFP144
D D1 A D3 A1 108 109 73 72
0.10mm .004 Seating Plane
A2
B
E3
E1
144 1 e 36
37 C L1
E
L
K
PQFP144
Millimeter Dimension Minimum A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 28/29 0.65 30.95 27.90 0.25 3.17 0.22 0.13 30.95 27.90 31.20 28.00 22.75 0.65 31.20 28.00 22.75 0.80 1.60 0 (minimum), 7 (maximum) 0.95 0.026 31.45 28.10 1.219 1.098 3.42 3.67 0.38 0.23 31.45 28.10 Typical Maximum 4.07 0.010 0.125 0.009 0.005 1.219 1.098 Minimum
Inch Typical Maximum 0.160
0.135
B
0.144 0.015 0.009
1.228 1.102 0.896 0.026 1.228 1.102 0.896 0.031 0.063
1.238 1.106
1.238 1.106
0.037
ST70135A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. STMicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http ://www.st.com
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